Integrated circuit devices generally include a large number of semiconductor devices such as transistors which are interconnected to perform predetermined functions. As is well known to those having skill in the art, the integration density of integrated circuits generally continues to increase, so that smaller and smaller devices are generally formed. The contact resistance of the electrical interconnects of the semiconductor devices should preferably be reduced as the integration density continues to increase.
The contact resistance of an interconnect is determined, at least in part, by the material which is used. Accordingly, many interconnect materials have been investigated for semiconductor devices. For example, a polycide contact, which is formed from polysilicon and a metal silicide, generally has a low contact resistance and excellent stability. Accordingly, polycides are widely used for interconnects for semiconductor devices. In particular, tungsten polycide including a polysilicon layer and a tungsten silicide layer, is widely used to form semiconductor device interconnects.
Unfortunately, polycide has a resistivity which is generally higher than that of a single metal. Tungsten polycide therefore may not be optimal for forming ohmic contacts with a silicon-based semiconductor device, such as N+ type and P+ type silicon. Accordingly, metal interconnects are being investigated as a replacement for polycide interconnects.
When a metal interconnect is used for a semiconductor device, it is important that the interconnect maintain stability and satisfactory electrical performance after annealing. For example, when tungsten is used as a metal interconnect for a semiconductor device, three layers are generally used. An ohmic contact region of titanium silicide is formed by reacting titanium with the silicon semiconductor device by annealing. A diffusion barrier layer formed of titanium nitride is deposited on the ohmic contact region. A conductive layer formed of tungsten is then deposited on the diffusion barrier.
The titanium silicide is generally formed by one of two processes. The first process forms titanium silicide having the meta-stable phase (C-49) using a first rapid thermal annealing (RTA) process of titanium at approximately 600.degree. C., followed by wet etching of the remaining titanium layer. The second process forms the titanium silicide layer by changing the titanium silicide layer in the meta-stable phase (C-49) to a stable phase (C-54) using a second RTA process at approximately 800.degree. C.
Unfortunately, in the process of forming a metal interconnect using a titanium silicide layer as described above, the electrical characteristics of the material may deteriorate. In particular, the titanium silicide layer which forms the ohmic contact region in the multi-layer contact is formed by a chemical reaction between silicon in the semiconductor device and titanium which is deposited thereon. Unfortunately, dopants from the silicon may diffuse through the interface between the silicon and the titanium. These dopants may continue to diffuse during the annealing process which forms the ohmic contact and their rate of diffusion generally increases as more heat is applied. The dopants tend to decrease the conductivity and increase the contact resistance of the metal interconnect.
Moreover, the high temperature annealing process may cause agglomeration of the titanium silicide in the ohmic contact region. As a result of this agglomeration, the conductive substrate thereby may come into direct contact with the diffusion barrier layer (for example titanium nitride). As the agglomeration increases, the contact resistance generally also increases.
FIG. 1 is a cross-sectional view of a metal interconnect for a semiconductor device. The contact of FIG. 1 may be formed by depositing a dielectric layer 15 on a semiconductor device 10. The dielectric layer includes a contact hole which exposes a portion of the semiconductor device. The semiconductor device preferably includes silicon, such as doped silicon or silicide. The contact hole may be formed by coating the dielectric layer 15 with a photoresist (not shown), photolithographically patterning the photoresist and then forming a contact hole by selectively etching the dielectric film and the exposed portion of the semiconductor device. The photoresist is then removed.
Continuing with the description of FIG. 1, a titanium layer is deposited on the dielectric film 15. A titanium silicide ohmic layer 20 is then formed having the meta-stable phase C-49, at the exposed portion of the semiconductor device 15. The titanium silicide ohmic contact 20 may be formed by performing a first rapid thermal annealing (RTA) process at approximately 600.degree. C. The remaining titanium layer is then removed using wet etching. The titanium silicide ohmic contact 20 is then converted to the C-54 stable phase by performing a second RTA process at approximately 800.degree. C. A diffusion barrier 25, for example titanium nitride, and a conductive layer 30, for example tungsten, are then deposited on the semiconductor device.
Unfortunately, dopants from the semiconductor device 10 may diffuse through the ohmic contact region 20 during the annealing process, and especially during the second RTA process which is performed at high temperature. This dopant diffusion may increase the contact resistance.
Moreover, the high temperature annealing process may cause agglomeration of the titanium silicide of the ohmic contact 20. Accordingly, the semiconductor device 10 containing silicon may directly connect with the diffusion barrier 25 comprising titanium nitride. The contact resistance may increase and the semiconductor device performance may degrade.
FIG. 2 is a line drawing of a TEM photograph which shows the agglomeration of titanium silicide of a metal interconnection structure of a conventional semiconductor device. As shown, a portion of the titanium silicide ohmic contact exhibits non-uniform thickness due to the agglomeration of the titanium silicide.
FIG. 3 graphically illustrates the contact resistance of a metal interconnection structure of a conventional semiconductor device as a function of annealing temperature and contact size. As shown, the contact resistance generally increases as the annealing temperature increases or the contact size decreases.
FIG. 4 graphically illustrates the contact resistance of a metal interconnect of a conventional semiconductor device. The specific example is an integrated circuit memory device bit line which contacts a silicon substrate and a gate line. The gate material, tungsten silicide, is widely used. Titanium silicide is formed by depositing a titanium layer on the tungsten silicide layer and annealing it at a predetermined temperature. As shown in FIG. 4, the contact resistance of the bit line and gate line generally increases as a function of the annealing processes. As also shown in FIG. 4, when titanium nitride is used instead of titanium on tungsten silicide, stable resistance can be provided regardless of annealing temperature.
Accordingly, notwithstanding the above improvements, a reduction of dopant diffusion and a reduction of agglomeration of an ohmic contact layer comprising titanium silicide is still needed, to provide high performance interconnects for semiconductor devices.